This invention relates generally to semiconductor technology and, more specifically, to the formation of MOS transistors with short, asymmetrical, channel regions and lightly doped drain extension regions formed through a double angled implantation process.
An important subject of ongoing research in the semiconductor industry is the reduction in the dimensions of devices used in integrated circuits. Planar transistors such as metal oxide semiconductor (MOS) transistors are particularly suited to use in high density integrated circuits. As the size of MOS transistors and other active devices decreases, the dimensions of the source/drain/gate electrodes, and the channel region of each device, must decrease correspondingly.
When fabricating MOS transistors, the source and drain electrodes are typically heavily doped to reduce the parasitic resistance of the device. While the doping improves conductance, it increases parasitic capacitance, and lowers the breakdown voltage. Many prior art devices interpose lightly doped drain ODD) regions on either side of the channel region, between the channel region and the source/drain electrodes. These LDD regions permit the MOS devices to develop adequate breakdown voltages. However, these LDD regions also increase the resistance between the source and drain when the transistor is turned on. This increased parasitic resistance degrades the switching speed and current carrying capabilities of the transistor. The necessity of LDD regions also adds process steps to fabrication which negatively affect both cost and reliability.
A MOS transistor suitable to control the gating and amplification of high speed signals must have a low parasitic capacitance, low parasitic resistance, and a breakdown voltage larger than the signals which are carried. These performance parameters represent design tradeoffs well known to those skilled in the art of MOS transistor fabrication.
Most prior art MOS transistors have channel regions that are substantially the same size as the overlying gate electrode. The channel region size and shape is a direct result of implanting dopants in the silicon underlying the gate electrode to form source/drain electrodes and LDD regions, after the deposition of the gate electrode. The wide channel region formed in such as process contribute undesirable characteristics to a transistor's performance. It is commonly acknowledged that the drain current is inversely proportional to the length of the channel.
Procedures exist in the prior art to implant the area under the gate electrode with dopant to change performance characteristics of the transistor. A tilted ion implant is performed to insure a good overlay between the gate the source electrodes. That is, to insure a portion of the source electrode underlies the gate. A halo implant is typically performed in the eight sides surrounding a gate electrode, preventing the occurrence of the short channel effect, or leakage current. However, these techniques have not been used to substantially change the size and position of the channel region underlying the gate electrode.
In a co-pending patent application, Ser. No. 08/918,678, entitled "Asymmetric Channel Doped MOS Structures and Method for Same", invented by Hsu et al., filed on Aug. 21, 1997, and assigned to the assignees of the instant application, a transistor structure and formation method were disclosed to form an asymmetric channel region through a single angled ion implantation. A drain extension region permits large break down voltage without source resistance. Further, the drain extension eliminates the need for lightly doped drain regions (LDD), so that process steps are saved.
It would be advantageous to provide a MOS transistor with a large breakdown voltage that is fabricated without LDD regions between the channel region and the source and drain electrodes, thereby reducing the parasitic resistance of the transistor.
It would be advantageous to provide a MOS transistor with a shorter channel length to permit the conduction of larger drain currents.
It would be advantageous to provide a MOS transistor with a higher switching speed and drain current carrying capabilities.
It would be advantageous to provide a MOS transistor with fewer fabrication steps, fewer implantations of dopant, and fewer barrier structures to improve reliability and lower costs.
It would be advantageous to provide a MOS transistor with an asymmetric channel, as described above, with a more heavily doped drain extension region to minimize drain resistance.
Accordingly, in the fabrication of transistors selected from the group consisting of NMOS and PMOS transistors, a method for forming asymmetric channel regions and drain extension regions has been provided. The method comprises the steps of.
a) isolating and doping a region of silicon in which the transistor is to be formed; PA1 b) forming a gate electrode region overlying the silicon region, the gate electrode region having a length extending from the source to the drain, and vertical sidewalls adjoining the source and drain; PA1 c) forming a channel region through a tilted implantation of dopant at a predetermined angle, into the silicon region underlying the gate on the source side to form a channel region having a length less than the gate length, the channel region extending from underneath the gate electrode vertical sidewall directly adjacent the source, toward the drain; and PA1 d) forming a drain extension through tilted implantation of dopant at a predetermined angle, into the silicon region underlying the gate on the drain side, the drain extension region extending from underneath the gate electrode vertical sidewall directly adjacent the drain, toward the source, whereby a transistor is formed with a high breakdown voltage and low source resistance. PA1 e) implanting a fourth dopant at a fourth ion dose and fourth ion energy level, to complete the formation of the gate, source and drain regions. PA1 f) depositing a layer of oxide over the source, drain, and gate regions of the transistor; PA1 g) forming contact holes through the oxide deposited in step e), to the source, drain, and gate regions; and PA1 h) depositing metal in the contact holes, forming independent electrical connections to the source, drain, and gate.
In some aspects of the invention, Step c) occurs before Step d). Alternately, Step d) occurs before Step c). Further steps, following Step d), include:
Typically, Step c) includes masking the drain region to prevent the implantation of dopant ions during step c). Likewise, Step d) includes masking the source region to prevent the implantation of dopant ions during step d). Steps c) and d) includes using an ion implantation angle in the range between 30.degree. and 70.degree., preferably 60.degree., from the vertical sidewall of the gate electrode adjoining the drain and source, respectively.
The above-described method is convenient for the fabrication of N+/P+ Dual Poly Gate CMOS transistors. Then, Step c) includes forming the channel region in the NMOS transistors while, simultaneously, forming the drain extension region in the PMOS transistors, and Step d) includes forming the drain extension in NMOS transistors while, simultaneously, forming the channel region in the PMOS transistors.
N+/P+ Dual Poly Gate CMOS transistors and MOS transistors, including NMOS and PMOS transistors, having asymmetric short channel regions, and drain extension regions have also been provided. The transistors comprise isolated silicon regions, including a source and a drain. Gate electrodes overlie the silicon regions with a length extending from the source to the drain. A silicon channel region having a channel length less than the gate length, underlies the gate and extends from the source, toward the drain. The channel region is formed by implanting ions of dopant at a predetermined angle, from the source side of the gate electrode, into the channel region. The transistor also comprises a silicon drain extension region extending underneath the gate from the drain, toward the channel region. The drain extension region is formed by implanting ions of dopant at a predetermined angle, from the drain side of the gate electrode, into the drain extension region. In this manner, the short channel region minimizes drain capacitance, and a lightly doped drain extension maximizes drain operation voltage.
Typically, the transistor includes a layer of oxide over the source, drain, and gate regions of the transistor with contact holes through the oxide, to the source, drain, and gate regions. Metal in the contact holes forms independent electrical connections to the source, drain, and gate, whereby the transistor is interfaced with other electrical circuits.
The NMOS drain and the PMOS source regions are masked during the angled ion implantation of the NMOS channel and the PMOS drain extension regions. Likewise, the NMOS source and the PMOS drain regions are masked during the angled ion implantation of the NMOS drain extension and PMOS channel regions.
The PMOS drain extension regions are formed by angled implantation of a dopant selected from the group consisting of boron and BF.sub.2. The ion dose is in the range between 1.times.10.sup.13 and 1.times.10.sup.15 /cm.sup.2. The ion energy level is in the range between 2 keV and 30 keV when the dopant is boron, and the ion energy level is in the range between 10 keV and 150 keV when the dopant is BF.sub.2. The NMOS drain extension regions are formed by implanting a dopant selected from the group consisting of phosphorus and arsenic. The ion dose is in the range between 1.times.10.sup.13 and 1.times.10.sup.15 /cm.sup.2. The ion energy level is in the range between 10 keV and 100 keV when the dopant is phosphorus, and the ion energy level is in the range between 20 keV and 200 keV when said dopant is arsenic.